1. Field of the Invention
The present invention relates to chip package technology, and in particular relates to a chip package and fabrication method thereof.
2. Description of the Related Art
A wafer level packaging technology for a chip package has been developed. A semiconductor wafer is usually bonded to a glass substrate with a spacing layer therebetween. After the wafer level packaging process is completed, a dicing process is performed between chips to form separated chip packages.
The CTE (coefficient of thermal expansion) mismatch between the semiconductor substrate, the spacing layer and the glass substrate causes reliability problems or even delamination of the chip package as the spacing layer cannot tightly adhere to the semiconductor substrate and/or the glass substrate. As a result, moisture or air may enter into the chip package, adversely affecting electrical performance thereof.
Hence, it is desirable to provide a chip package which can overcome the problems described above to improve the reliability of the chip package.